IBM PowerPC 403GCX
The programmable interval timer is a 32-bit regis-
ter that is decremented at the same rate as the
time base is incremented. The user preloads the
PIT register with a value to create the desired
delay. When the register is decremented to
zeros, the timer stops decrementing, a bit is set
in the timer status register (TSR), and a PIT inter-
rupt is generated. Optionally, the PIT can be pro-
grammed to reload automatically the last value
written to the PIT register, after which the PIT
begins decrementing again.The timer control
register (TCR) contains the interrupt enable for
the PIT interrupt.
break and false start bit detection are also pro-
vided, as well as operating modes that allow the
serial port to react to handshaking line inputs or
control handshaking line outputs without soft-
ware interaction. Program generation mode
allows the serial port transmitter to be used for
pulse width modulation with duty cycle variation
controlled by frame size, baud rate, and data pat-
tern.
JTAG Port
The JTAG port has been enhanced to allow it to
be used as a debug port. Through the JTAG test
access port, debug software on a workstation or
PC can single-step the processor and interrogate
internal processor state to facilitate software
debugging. The standard JTAG boundary-scan
register allows testing of circuitry external to the
chip, primarily the board interconnect. Alterna-
tively, the JTAG bypass register can be selected
when no other test data register needs to be
accessed during a board-level test operation.
The fixed interval timer generates periodic inter-
rupts based on selected bits in the time base.
Users may select one of four intervals for the
timer period by setting the correct bits in the
TCR. When the selected bit in the time base
changes from 0 to 1, a bit is set in the TSR and a
FIT interrupt is generated. The FIT interrupt
enable is contained in the TCR.
The watchdog timer generates a periodic inter-
rupt based on selected bits in the time base.
Users may select one of four time periods for the
interval and the type of reset generated if the
watchdog timer expires twice without an interven-
ing clear from software. If enabled, the watchdog
timer generates a system reset unless an excep-
tion handler updates the watchdog timer status
bit before the timer has completed two of the
selected timer intervals.
Real-Time Debug Port
The real-time debug port supports tracing the
instruction stream being executed out of the
instruction cache in real time. The trace status
signals provide trace information while in real-
time trace debug mode. This mode does not alter
the performance of the processor.
P/N Code
Table 3. PPC403GCX Part Number
Serial Port
MHz
Part Number
Package
The 403GCX serial port is capable of supporting
RS232 standard serial communication, as well as
high-speed execution (bit speed at a maximum of
one-sixteenth of the SysClk processor clock
rate). The serial clock which drives the serial port
can come from the internal SysClk or an external
clock source at the external serial clock pin (max-
imum of one-half the SysClk rate).
50
403GCX-3JC50C2
403GCX-3BC50C2
PQFP
PBGA
66
80
403GCX-3JC66C2
403GCX-3BC66C2
PQFP
PBGA
403GCX-3JC80C2
403GCX-3BC80C2
403GCX-3JC80C2A
403GCX-3BC80C2A
PQFP
PBGA
PQFP
PBGA
The 403GCX serial port contains many features
found only on advanced communications control-
lers, including the capability of being a peripheral
for DMA transfers. An internal loopback mode
supports diagnostic testing without requiring
external hardware. An auto echo mode is
Notes:
1. The dash number indicates the speed version.
2. The characters in the dash number indicate reliabil-
ity grade (3), package type (J or B), revision level
(C), maximum internal CPU core clock rate, com-
mercial version (C), and the ratio of internal CPU
included to retransmit received bits to the exter-
nal device. Auto-resynchronization after a line
6
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