IBM PowerPC 403GCX
updated to reflect the new context of the
machine. The new MSR contents take effect
beginning with the first instruction of the excep-
tion handling routine.
Asynchronous imprecise exceptions include sys-
tem resets and machine checks. Synchronous
precise exceptions include most debug excep-
tions, program exceptions, data storage viola-
tions, TLB misses, system calls, and alignment
error exceptions. Asynchronous precise excep-
tions include the critical interrupt exception,
external interrupts, and internal timer facility
exceptions and some debug events.
At the end of the exception handling routine, exe-
cution of a return from interrupt (rfi) instruction
forces the contents of SRR0 and SRR1 to be
loaded into the program counter and the MSR,
respectively. Execution then begins at the
address in the program counter.
The four critical exceptions are processed in a
similar manner. When a critical exception is
taken, SRR2 and SRR3 hold the next sequential
address to be processed when returning from the
exception and the contents of the machine state
register, respectively. After the critical exception
handling routine, return from critical interrupt
(rfci) forces the contents of SRR2 and SRR3 to
be loaded into the program counter and the
MSR, respectively.
Only one exception is handled at a time. If multi-
ple exceptions occur simultaneously, they are
handled in priority order.
The 403GCX processes exceptions as reset, crit-
ical, or noncritical. Four exceptions are defined
as critical: machine check exceptions, debug
exceptions, exceptions caused by an active level
on the critical interrupt pin, and the first time-out
from the watchdog timer.
When a noncritical exception is taken, special
purpose register Save/Restore 0 (SRR0) is
loaded with the address of the excepting instruc-
tion (synchronous exceptions other than system
call) or the next sequential instruction to be pro-
cessed (asynchronous exceptions and system
call). If the 403GCX is executing a multicycle
instruction (load/store multiple, load/store string,
multiply or divide), the instruction is terminated
and its address stored in SRR0. Save/Restore
Register 1 (SRR1) is loaded with the contents of
the machine state register. The MSR is then
Timers
The 403GCX contains four timer functions: a
time base, a programmable interval timer (PIT), a
fixed interval timer (FIT), and a watchdog timer.
The time base is a 64-bit counter incremented at
the timer clock rate. The timer clock may be
driven by either an internal signal equal to the
processor clock rate or by a separate external
timer clock pin. No interrupts are generated when
the time base rolls over.
Table 2. 403GCX Exception Priorities, Types and Classes
Priority
Exception Type
Exception Class
1
2
System Reset
Asynchronous imprecise
Asynchronous imprecise
Machine Check
Synchronous precise
(except UDE and EXC)
3
Debug
4
5
Critical Interrupt
Asynchronous precise
Asynchronous precise
WatchdogTimer Time-out
Program Exception, Data Storage Exception,TLB Miss, and Synchronous precise
System Calls
6
7
8
Alignment Exceptions
External Interrupts
Synchronous precise
Asynchronous precise
Asynchronous precise
Asynchronous precise
9
Fixed Interval Timer
10
Programmable Interval Timer
5
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