IBM PowerPC 403GCX
size.
Instruction Cache Unit
The instruction cache unit (ICU) is a two-way set-
associative 16KB cache memory unit with
enhancements to support branch prediction and
folding. The ICU is organized as 512 sets of 2
lines, each line containing 16 bytes. A separate
bypass path is available to handle cache-inhib-
ited instructions and to improve performance dur-
ing line fill operations.
The cache can send two cached instructions per
cycle to the execution unit, allowing instructions
to be folded out of the queue without interrupting
normal instruction flow. When a branch instruc-
tion is folded and executed in parallel with
another instruction, the ICU provides two more
instructions to replace both of the instructions
just executed so that bandwidth is balanced
between the ICU and the execution unit.
at the requested fullword, continuing to the end of
the block and then wrapping around to fill the
remaining fullwords at the beginning of the block.
DMA Controller
The four-channel DMA controller manages block
data transfers in buffered, fly-by and memory-to-
memory transfer modes with options for burst-
mode operation. In fly-by and buffered modes,
the DMA controller supports transactions
between memory and peripheral devices.
Each DMA channel provides a control register, a
source address register, a destination address
register, a transfer count register, and a chained
count register. Peripheral set-up cycles, wait
cycles, and hold cycles can be programmed into
each DMA channel control register. Each chan-
nel supports chaining operations. The DMA sta-
tus register holds the status of all four channels.
Exception Handling
Table 2 summarizes the 403GCX exception prior-
ities, types, and classes. Exceptions are gener-
ated by interrupts from internal and external
peripherals, instructions, the internal timer facility,
debug events or error conditions. Six external
interrupt signals are provided on the 403GCX:
one critical and five general-purpose, all individu-
ally maskable.
All exceptions fall into three basic classes: asyn-
chronous imprecise exceptions, synchronous
precise exceptions, and asynchronous precise
exceptions. Asynchronous exceptions are
caused by events external to processor execu-
tion, while synchronous exceptions are caused
by instructions.
Except for a system reset or machine check, all
403GCX exceptions are handled precisely. Pre-
cise handling implies that the address of the
excepting instruction (synchronous exceptions
other than system call) or the address of the next
sequential instruction (asynchronous exceptions
and system call) is passed to the exception han-
dling routine. Precise handling also implies that
all instructions prior to the excepting instruction
have completed execution and have written back
their results.
Data Cache Unit
The data cache unit is provided to minimize the
access time of frequently used data items in main
store. The 8KB cache is organized as a two-way
set associative cache. There are 256 sets of 2
lines, each line containing 16 bytes of data. The
cache features byte-writeability to improve the
performance of byte and halfword store opera-
tions.
Cache operations are performed using a write-
back strategy. A write-back cache only updates
locations in main storage that corresponds to
changed locations in the cache. Data is flushed
from the cache to main storage whenever
changed data needs to be removed from the
cache to make room for other data.
The data cache may be disabled for a 128MB
memory region via control bits in the data cache
control register or on a per-page basis if the
MMU is enabled for data translation. A separate
bypass path is available to handle cache-inhib-
ited data operations and to improve performance
during line fill operations.
Cache flushing and filling are triggered by load,
store, and cache control instructions executed by
the processor. Cache blocks are loaded starting
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