IBM11N1645L
IBM11N1735Q
1M x 64/72 DRAM Module
Read Cycle
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tRCD
tRSH
tCRP
VIH
CAS
tCAS
VIL
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH
Address
VIL
Row
Column
tRCH
tRRH
tWRP
tWRH
tRCS
VIH
WE
VIL
NOTE 1
tAA
tOES
VIH
tOEA
OE
VIL
tDZC
tCDD
tDZO
tODD
VIH
DIN
VIL
Hi-Z
tCAC
tCLZ
tOFF
tOEZ
VOH
DOUT
Hi-Z
Valid Data Out
Hi-Z
VOL
tRAC
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H”: or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H8035
SA14-4630-02
Revised 5/96
Page 13 of 33
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