IBM11N1645L
IBM11N1735Q
1M x 64/72 DRAM Module
Read-Modify-Write-Cycle
tRWC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRSH
VIH
tCAS
CAS
tRAD
VIL
tASR
tASC
tRAH
tCAH
VIH
VIL
Address
Row
Column
tCWD
tRWL
tCWL
tAWD
tWRH
tWRP
tRWD
tWP
VIH
VIL
NOTE 1
tAA
WE
OE
tRCS
tOEH
VIH
VIL
tOEA
tDZC
tDH
tDS
tDZO
VIH
VIL
DIN
Hi-Z
tCAC
DIN
tODD
tCLZ
tOEZ
VOH
VOL
*
Hi-Z
Hi-Z
DOUT
DOUT
*
tRAC
t
OEH greater than or equal to tCWL
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H8035
SA14-4630-02
Revised 5/96
Page 16 of 33
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