IBM11N1645L
IBM11N1735Q
1M x 64/72 DRAM Module
EDO Page Mode Read Cycle
tRP
tRASP
VIH
RAS
tCPRH
VIL
tCRP
tHPC
tRCD
tCP
tCP
tRSH
tHCAS
tHCAS
tHCAS
VIH
VIL
CAS
tCSH
tASC
tRAL
tCAH
tASR tRAH
tCAH
tASC
tCAH
tASC
VIH
VIL
Address
Row
Column 1
Column 2
Column N
tRAD
tRCH
tRRH
tWRH
tWRP
tRCS
VIH
VIL
WE
NOTE 1
tWP
tCAC
tCAC
tCPA
tCPA
tOFF
tOES
tOEA
tAA
tAA
VIH
VIL
OE
tOEZ
tRAC
tAA
tDOH
tDOH
tCAC
tCLZ
VOH
VOL
DOUT
Hi-Z
Data Out 1
Data Out 2
Data Out N
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H8035
SA14-4630-02
Revised 5/96
Page 17 of 33
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