IBM11D1475B IBM11D2475B
IBM11E1475B IBM11E2475B
1M/2M x 32 Desktop ECC-on-SIMM
Read Cycle
tRC
tRAS
tRP
VIH
tAR
RAS
VIL
tCSH
tRCD
tRSH
tCRP
VIH
CAS
VIL
tCAS
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH
Address
Row
Column
VIL
tRCH
tRRH
tWRP
tWRH
tRCS
VIH
VIL
NOTE 1
WE
tAA
tDZC
tCDD
VIH
VIL
DIN
Hi-Z
tCAC
tCLZ
tOFF
VOH
VOL
DOUT
Hi-Z
Valid Data Out
Hi-Z
tRAC
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
75H3507
SA14-4343-00
Released 6/96
Page 10 of 22
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