IBM041811TLAB
IBM043611TLAB
32K x 36 & 64K x 18 SRAM
Preliminary
Clock Truth Table
K
ZZ
L
SS
L
SW
H
L
SBWa
SBWb
SBWc
SBWd
DQ (n)
DQ (n+1)
MODE
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
X
D
0-35
0-8
X
L
X
H
L
X
H
H
L
X
H
H
H
L
X
Read Cycle All Bytes
Write Cycle 1st Byte
Write Cycle 2nd Byte
Write Cycle 3rd Byte
Write Cycle 4th Byte
Write Cycle All Bytes
Abort Write Cycle
Deselect Cycle
OUT
D
IN
L
L
X
D
9-17
18-26
27-35
0-35
L
L
L
H
H
H
L
X
IN
D
IN
L
L
L
H
H
L
X
D
IN
L
L
L
H
L
X
D
L
L
L
L
X
X
IN
L
L
L
H
X
X
H
X
X
H
X
X
H
X
X
High-Z
High-Z
High-Z
L
H
X
X
X
X
H
High-Z
Sleep Mode
Output Enable Truth Table
Operation
Read
G
L
DQ
D
0-35
OUT
Read
H
X
X
X
High-Z
High-Z
High-Z
High-Z
Sleep (ZZ = H)
Write (SW = L)
Deselect (SS = H)
Absolute Maximum Ratings
Item
Power Supply Voltage
Output Power Supply Voltage
Input Voltage
Symbol
Rating
Units
V
Notes
V
DD
-0.5 to 4.0
-0.5 to 4.0
1
1
1
1
1
1
1
1
V
DDQ
V
V
IN
-0.5 to V +0.5
V
DD
V
OUT
-0.5 to V +0.5
Output Voltage
V
DD
T
A
°C
°C
°C
mA
Operating Temperature
Junction Temperature
Storage Temperature
Short Circuit Output Current
0 to +70
110
T
J
T
-55 to +125
25
STG
I
OUT
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
77H9965.T5
10/98
Page 6 of 22
IBM [ IBM ]
