IBM041811TLAB
IBM043611TLAB
Preliminary
32K x 36 & 64K x 18 SRAM
Pin Description
SA0-SA15
DQ0-DQ35
K, K
Address Input
G
SS
Asynchronous Output Enable
Data I/O
Synchronous Select
Differential Input-Register Clocks
Write Enable, Global
M1, M2
Mode Inputs- Selects Read Protocol Operation.
GTL/HSTL Input Reference Voltage
V
(2)
SW
REF
V
SBWa
SBWb
Write Enable, Byte a (DQ0-DQ8)
Write Enable, Byte b (DQ9-DQ17)
Power Supply (+3.3V)
Ground
DD
V
SS
V
SBWc
SBWd
Write Enable, Byte c (DQ18-DQ26)
Write Enable, Byte d (DQ27-DQ35)
IEEE 1149.1 Test Inputs (LVTTL levels)
IEEE 1149.1 Test Output (LVTTL level)
Output Power Supply
Asynchronous Sleep Mode
Output Driver Impedance Control
No Connect
DDQ
ZZ
ZQ
NC
TMS,TDI,TCK
TDO
Block Diagram
SA0-SA15
K
SS
ZZ
RD Add
Register
WR Add
Register
32K x 36
or
Latch
64K x 18
Array
SW
Register
SW
Register
SW
Column Decode
Read/Write Amp
SBW
SBW
Register
SBW
Register
Latch
Write
2:1 MUX
Buffer
Data Out
Register
SS
Register
SS
Register
G
DQ0-DQ35
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
77H9965.T5
10/98
Page 3 of 22
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