IBM041811TLAB
IBM043611TLAB
Preliminary
32K x 36 & 64K x 18 SRAM
Power-Up/ Power-Down Sequencing
The Power supplies need to be powered up in the following manner: V , V
, V
, and Inputs. The
REF
DD
DDQ
power-down sequencing must be the reverse. V
must never be allowed to exceed V
.
DDQ
DD
Ordering Information
Part Number
Organization
Speed
Leads
IBM041811TLAB - 4
IBM041811TLAB - 4N
IBM041811TLAB - 5
IBM041811TLAB - 6
IBM041811TLAB - 7
IBM043611TLAB - 4
IBM043611TLAB - 4N
IBM043611TLAB - 5
IBM043611TLAB - 6
IBM043611TLAB -7
64K x 18
64K x 18
64K x 18
64K x 18
64K x 18
32K x 36
32K x 36
32K x 36
32K x 36
32K x 36
2.1ns Access / 4.0ns Cycle
2.25ns Access / 4.3ns Cycle
2.5ns Access / 5ns Cycle
3.0ns Access / 6ns Cycle
3.0ns Access / 7.0ns Cycle
2.1ns Access / 4.0ns Cycle
2.25ns Access / 4.3ns Cycle
2.5ns Access / 5ns Cycle
3.0ns Access / 6ns Cycle
3.0ns Access / 7.0ns Cycle
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
77H9965.T5
10/98
Page 5 of 22
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