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IBM041811TLAB-6 参数 Datasheet PDF下载

IBM041811TLAB-6图片预览
型号: IBM041811TLAB-6
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 64KX18, 3ns, CMOS, PBGA119, BGA-119]
分类和应用: 时钟静态存储器内存集成电路
文件页数/大小: 22 页 / 163 K
品牌: IBM [ IBM ]
 浏览型号IBM041811TLAB-6的Datasheet PDF文件第6页浏览型号IBM041811TLAB-6的Datasheet PDF文件第7页浏览型号IBM041811TLAB-6的Datasheet PDF文件第8页浏览型号IBM041811TLAB-6的Datasheet PDF文件第9页浏览型号IBM041811TLAB-6的Datasheet PDF文件第11页浏览型号IBM041811TLAB-6的Datasheet PDF文件第12页浏览型号IBM041811TLAB-6的Datasheet PDF文件第13页浏览型号IBM041811TLAB-6的Datasheet PDF文件第14页  
IBM041811TLAB  
IBM043611TLAB  
32K x 36 & 64K x 18 SRAM  
Preliminary  
AC Characteristics (TA = 0 to +70°C, VDD = 3.3V 5% + 10%)  
-4  
-4N  
-5  
-6  
-7  
Parameter  
Symbol  
Units  
Notes  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
t
Cycle Time  
4.0  
1.5  
1.5  
4.3  
1.5  
1.5  
5.0  
1.5  
1.5  
6.0  
1.5  
1.5  
7.0  
1.5  
1.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
KHKH  
KHKL  
KLKH  
KHQV  
AVKH  
KHAX  
SVKH  
KHSX  
WVKH  
KHWX  
DVKH  
KHDX  
KHQX  
KHQZ  
KHQX4  
GHQZ  
GLQX  
GLQV  
GHKH  
KHGX  
GHGL  
ZZR  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Clock High Pulse Width  
Clock Low Pulse Width  
Clock to Output Valid  
2.1  
2.25  
2.5  
3.0  
3.0  
1
4
Address Setup Time  
0.4  
0.75  
0.5  
1.0  
0.5  
1.0  
0.5  
0.75  
0.5  
0.4  
0.75  
0.5  
1.0  
0.5  
1.0  
0.5  
0.75  
0.5  
0.5  
1.0  
0.5  
1.0  
0.5  
1.0  
0.5  
1.0  
0.5  
0.5  
1.0  
0.5  
1.0  
0.5  
1.0  
0.5  
1.0  
1.0  
0.5  
1.0  
0.5  
1.0  
0.5  
1.0  
0.5  
1.0  
1.0  
Address Hold Time  
Sync Select Setup Time  
Sync Select Hold Time  
Write Enables Setup Time  
Write Enables Hold Time  
Data In Setup Time  
Data In Hold Time  
Data Out Hold Time  
1, 3, 4  
Clock High to Output High-Z  
Clock High to Output Active  
Output Enable to High-Z  
Output Enable to Low-Z  
Output Enable to Output Valid  
Output Enable Set-up Time  
Output Enable Hold TIme  
Output Enable Pulse High  
Sleep Mode Recovery Time  
Sleep Mode Enable Time  
2.25  
2.25  
2.5  
3.0  
3.5  
1
1
1
1
1
2
2
2
0.5  
0.5  
0.5  
0.7  
0.7  
2.0  
2.0  
2.5  
2.5  
3.5  
0.3  
0.3  
0.3  
0.3  
0.3  
2.0  
2.0  
2.5  
2.5  
3.5  
0.5  
1.3  
1.75  
200  
0.5  
1.3  
1.75  
200  
0.5  
1.5  
2.0  
200  
0.5  
1.5  
2.5  
200  
0.5  
1.5  
2.5  
200  
8.0  
8.0  
10.0  
12.0  
14.0  
ZZE  
1. See AC Test Loading figure on page 11.  
2. Output Driver Impedance update specifications for G induced updates. Write and Deselect cycles will also induce Output Driver  
updates during High-Z.  
3. For 4 and 4N sorts, this spec is guaranteed by design to 0.7ns. Tested at 0.7ns.  
4. For 4 and 4N sorts, this spec is guaranteed by design to 0.4ns. Tested at 0.3ns  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
77H9965.T5  
10/98  
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