IBM041811TLAB
IBM043611TLAB
32K x 36 & 64K x 18 SRAM
Preliminary
SRAM Features
Late Write
Late Write function allows for write data to be registered one cycle after addresses and controls. This feature
eliminates one bus-turnaround cycle necessary when going from a Read to a Write operation. Late Write is
accomplished by buffering write addresses and data so that the write operation occurs during the next write
cycle. When a read cycle occurs after a write cycle, the address and write data information are stored tempo-
rarily in holding registers. During the first write cycle preceded by a read cycle, the SRAM array will be
updated with address and data from the holding registers. Read cycle addresses are monitored to determine
if read data is to be supplied from the SRAM array or the write buffer. The bypassing of the SRAM array
occurs on a byte-by-byte basis. When only one byte is written during a write cycle, read data from the last
written address will have new byte data from the write buffer and remaining bytes from the SRAM array.
Mode Control
Mode control pins M1 and M2 are used to select four different JEDEC standard read protocols. The SRAM
supports the following protocols:
• Single Clock, Flow-Through (M1 = V , M2 = V
)
SS
SS
• Pipeline (M1 = V , M2 = V
)
DD
SS
• Register-Latch (M1 = V , M2 = V
)
SS
DD
• Dual Clock, Flow-Through (M1 = V , M2 = V
)
DD
DD
This datasheet only describes Pipeline functionality. Mode control inputs must be set with power-up and must
not change during SRAM operation. Dual Clock will not be offered.
Sleep Mode
Sleep Mode is enabled by switching asynchronous signal ZZ High. When the SRAM is in Sleep mode, the
outputs will go to a High-Z state and the SRAM will draw standby current. SRAM data will be preserved and a
recovery time (t
) is required before the SRAM resumes to normal operation.
ZZR
Programmable Impedance/Power-Up Requirements
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V to allow for the
SS
SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line
impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a toler-
ance of TBD% is between 175W and 350W. Periodic readjustment of the output driver impedance is neces-
sary as the impedance is greatly affected by drifts in supply voltage and temperature. One evaluation occurs
every 64 clock cycles and each evaluation may move the output driver impedance level only one step at a
time towards the optimum level. The output driver has 32 discrete binary weighted steps. The impedance
update of the output driver occurs when the SRAM is in High-Z. Write and Deselect operations will synchro-
nously switch the SRAM into and out of High-Z, triggering an update. The user may choose to invoke asyn-
chronous G updates by providing a G setup and hold about the K Clock to guarantee the proper update. In
order to guarantee the optimum internally regulated supply voltage, the SRAM requires 4µs of power-up time
after V reaches its operating range. Furthermore, 2048 cycles followed by a Low-Z to High-Z transition are
DD
required to guarantee optimum output driver impedance.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
77H9965.T5
10/98
Page 4 of 22
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