IBM043611QLAB
IBM041811QLAB
32K X 36 & 64K X 18 SRAM
Preliminary
SRAM FEATURES
Late Write
Late Write function allows for write data to be registered one cycle after addresses and controls. This feature
eliminates one bus-turnaround cycle necessary when going from a Read to a Write operation. Late Write is
accomplished by buffering write addresses and data so that the write operation occurs during the next write
cycle. In the case a read cycle occurs after a write cycle, the address and write data information are stored tem-
porarily in holding registers. During the first write cycle preceded by a read cycle, the SRAM array will be
updated with the address and data from the holding registers. Read cycle addresses are monitored to deter-
mine if read data is to be supplied from the SRAM array or the write buffer. The bypassing of the SRAM array
data occurs on a byte by byte basis. When one byte is written during a write cycle, read data from the last writ-
ten address will have new byte data from the write buffer and remaining bytes from the SRAM array.
Mode Control
Mode control pins: M1 and M2 are used to select four different JEDEC standard read protocols. This SRAM
only supports the Single Clock, Pipeline protocol (M1 = V , M2 = V ). Mode control inputs must be set with
SS
DD
power up and must not change during SRAM operation.
Sleep Mode
Sleep mode is accomplished by switching asynchronous signal ZZ high. When the SRAM is in Sleep Mode, the
outputs will go to a High-Z state and the SRAM will draw standby current. SRAM data will be preserved and a
recovery time (t
) is required before the SRAM resumes to normal operation.
ZZR
Programmable Impedance/Power Up Requirements
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V to allow for the SRAM
SS
to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance
driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of 25% is
between 185Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance
is greatly affected by drifts in supply voltage and temperature. One evaluation occurs every 64 clock cycles and
each evaluation may move the output driver impedance level only one step at a time towards the optimum
level. The output driver has 16 discrete binary weighted steps. The impedance update of the output driver
occurs when the SRAM is in High-Z. Write and Deselect operations will synchronously switch the SRAM into
and out of High-Z, therefore, triggering an update. The user may choose to invoke asynchronous G updates by
providing a G setup and hold about the K Clock to guarantee the proper update. There are no power up
requirements for the SRAM; however, to guarantee optimum output driver impedance after power up, the
SRAM needs 1024 clock cycles followed by a Low-Z to High-Z transition.
Power-Up/ Power-Down Sequencing
The Power supplies need to be powered up in the following manner: V , V
, V and Inputs. The power
REF
DD
DDQ
down sequencing must be the reverse. V
must never be allowed to exceed V
.
DD
DDQ
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
03H9040
SA14-4659-04
Revised 7/96
Page 4 of 21
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