IBM043611QLAB
IBM041811QLAB
Preliminary
32K X 36 & 64K X 18 SRAM
Pin Description
SA0-SA15
DQ0-DQ35
Address Input
G
Asynchronous Output Enable
Data I/O
SS
Synchronous Select
Clock Mode Inputs - Selects Single or Dual
Clock Operation
K, K
Differential Input Register Clocks
M1, M2
VREF(2)
VDD
VSS
SW
SBWa
Write Enable, Global
GTL/HSTL Input Reference Voltage
Power Supply (+3.3V)
Ground
Write Enable, Byte a (DQ0-DQ8)
Write Enable, Byte b (DQ9-DQ17)
Write Enable, Byte c (DQ18-DQ26)
Write Enable, Byte d (DQ27-DQ35)
IEEE 1149.1 Test Inputs (LVTTL levels)
IEEE 1149.1 Test Output (LVTTL level)
SBWb
VDDQ
ZZ
SBWc
Output Power Supply
Asynchronous Sleep Mode
Output Driver Impedance Control
No Connect
SBWd
TMS,TDI,TCK
TDO
ZQ
NC
Block Diagram
SA0-SA15
K
SS
ZZ
RD Add
Register
WR Add
Register
32Kx36
or
Latch
64K x18
Array
SW
Register
SW
Register
SW
Column Decoder
Read/Write Amp
SBW
SBW
Register
SBW
Register
Latch
Write
2:1 MUX
Buffer
Data Out
Register
SS
Register
SS
Register
G
DQ0-DQ35
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
03H9040
SA14-4659-04
Revised 7/96
Page 3 of 21
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