欢迎访问ic37.com |
会员登录 免费注册
发布采购

IBM041811QLAB-7 参数 Datasheet PDF下载

IBM041811QLAB-7图片预览
型号: IBM041811QLAB-7
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 64KX18, 3.5ns, CMOS, PBGA119, BGA-119]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 21 页 / 301 K
品牌: IBM [ IBM ]
 浏览型号IBM041811QLAB-7的Datasheet PDF文件第5页浏览型号IBM041811QLAB-7的Datasheet PDF文件第6页浏览型号IBM041811QLAB-7的Datasheet PDF文件第7页浏览型号IBM041811QLAB-7的Datasheet PDF文件第8页浏览型号IBM041811QLAB-7的Datasheet PDF文件第10页浏览型号IBM041811QLAB-7的Datasheet PDF文件第11页浏览型号IBM041811QLAB-7的Datasheet PDF文件第12页浏览型号IBM041811QLAB-7的Datasheet PDF文件第13页  
IBM043611QLAB  
IBM041811QLAB  
Preliminary  
32K X 36 & 64K X 18 SRAM  
AC Characteristics (T =0 to +70°C, V =3.3 5% + 10% V)  
A
DD  
-5  
-6  
-7  
Parameter  
Symbol  
Units  
Notes  
Min.  
Max.  
2.5  
2.5  
2.5  
2.5  
5
Min.  
6.0  
1.5  
1.5  
Max.  
3.0  
3.0  
3.0  
3.0  
6
Min.  
7.0  
1.5  
1.5  
Max.  
3.5  
3.5  
3.5  
3.5  
7
tKHKH  
tKHKL  
tKLKH  
tKHQV  
tAVKH  
tKHAX  
tSVKH  
tKHSX  
tWVKH  
tKHWX  
tDVKH  
tKHDX  
tKHQX  
tKHQZ  
tKHQX4  
tGHQZ  
tGLQX  
tGLQV  
tGHKH  
tKHGX  
tZZR  
Cycle Time  
5.0  
1.5  
1.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Clock High Pulse Width  
Clock Low Pulse Width  
Clock to Output Valid  
1
Address Setup Time  
0.5  
1.0  
0.5  
1.0  
0.5  
1.0  
0.5  
1.0  
0.85  
0.5  
1.0  
0.5  
1.0  
0.5  
1.0  
0.5  
1.0  
0.85  
0.5  
1.0  
0.5  
1.0  
0.5  
1.0  
0.5  
1.0  
0.85  
Address Hold Time  
Sync Select Setup Time  
Sync Select Hold Time  
Write Enables Setup Time  
Write Enables Hold Time  
Data In Setup Time  
Data In Hold Time  
Data Out Hold Time  
1
1
Clock High to Output High-Z  
Clock High to Output Active  
Output Enable to High-Z  
Output Enable to Low-Z  
Output Enable to Output Valid  
Output Enable Set-up Time  
Output Enable Hold TIme  
Sleep Mode Recovery TIme  
Sleep Mode Enable TIme  
1.0  
1.0  
1.0  
1
1
0.5  
0.5  
0.5  
1
1
0.5  
1.5  
5
0.5  
1.5  
6
0.5  
1.5  
7
1, 2  
1, 2  
tZZE  
1. See AC Test Loading figure on page 8.  
2. Output Driver Impedance update specifications for G induced updates. Write and Deselect cycles will also induce Output Driver  
updates during High-Z.  
©IBM Corporation, 1996. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
03H9040  
SA14-4659-04  
Revised 7/96  
Page 9 of 21  
 
 复制成功!