IBM043611QLAB
IBM041811QLAB
32K X 36 & 64K X 18 SRAM
Preliminary
Clock Truth Table
K
ZZ
L
SS
L
SW
H
L
SBWa SBWb SBWc SBWd DQ (n) DQ (n+1)
MODE
Notes
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
X
DOUT 0-35
IN 0-8
DIN 9-17
X
L
X
H
L
X
H
H
L
X
H
H
H
L
X
Read Cycle All Bytes
Write Cycle 1st Byte
Write Cycle 2nd Byte
Write Cycle 3rd Byte
Write Cycle 4th Byte
Write Cycle All Bytes
Abort Write Cycle
Deselect Cycle
D
L
L
X
L
L
L
H
H
H
L
X
D
IN 18-26
IN 27-35
L
L
L
H
H
L
X
1
1
D
L
L
L
H
L
X
D
IN 0-35
L
L
L
L
X
X
L
L
L
H
X
X
H
X
X
H
X
X
H
X
X
High-Z
High-Z
High-Z
L
H
X
X
X
X
H
High-Z
Sleep Mode
1. x36 only.
Output Enable Truth Table
Operation
Read
G
L
DQ
DOUT 0-35
High-Z
High-Z
High-Z
High-Z
Read
H
X
X
X
Sleep (ZZ=H)
Write (SW=L)
Deselect (SS=H)
Absolute Maximum Ratings
Item
Power Supply Voltage
Input Voltage
Symbol
VDD
Rating
Units
V
Notes
-0.5 to 4.6
-0.5 to VDD+0.5
-0.5 to VDD+0.5
0 to +70
1
1
1
1
1
1
1
VIN
V
VOUT
TA
Output Voltage
V
° C
°C
° C
mA
Operating Temperature
Junction Temperature
Storage Temperature
Short Circuit Output Current
TJ
110
TSTG
IOUT
-55 to +125
25
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
03H9040
SA14-4659-04
Revised 7/96
Page 6 of 21
IBM [ IBM ]
