.
Preliminary
Features
• 32K x 36 or 64K x 18 Organizations
• 0.5 Micron CMOS Technology
• Synchronous Pipeline Mode Of Operation with
Self-Timed Late Write
• Single Differential GTL/HSTL Clock
• Single +3.3V Power Supply and Ground
• GTL/HSTL Input and Output levels
• Registered Addresses, Write Enables, Synchro-
nous Select and Data Ins.
• Registered Outputs
IBM043611QLAB
IBM041811QLAB
32K X 36 & 64K X 18 SRAM
• Common I/O
• Asynchronous Output Enable and Power Down
Inputs
• Boundary Scan using limited set of JTAG 1149.1
functions
• Byte Write Capability & Global Write Enable
• 7 X 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
• Programmable Impedance Output Drivers
Description
The IBM043611QLA and IBM041811QLA 1Mb
SRAM
S
are Synchronous Pipeline Mode, high per-
formance CMOS Static Random Access Memories
that are versatile, wide I/O, and achieves 5 nsec
cycle times. Differential K clocks are used to initiate
the read/write operation and all internal operations
are self-timed. At the rising edge of the K Clock, all
Addresses, Write-Enables, Sync Select and Data
Ins are registered internally. Data Outs are updated
from output registers off the next rising edge of the K
clock. An internal Write buffer allows write data to
follow one cycle after addresses and controls. The
chip is operated with a single +3.3V power supply
and is compatible with GTL/HSTL I/O interfaces.
03H9040
SA14-4659-04
Revised 7/96
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
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