Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM must be used to avoid data contention on the data bus
by placing the chip output drivers in a high impedance state at least one clock cycle before the Write Com-
mand is initiated. To insure the chip output drivers are tri-stated one cycle before the write operation begins,
DQM must be activated at least 3 clock cycles before the Write Command and be deactivated in the same
clock cycle as the Write Command.
Read Interrupted by a Write (Burst Length = 4, CAS Latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
: “H” or “L”
DQM
READ A
NOP
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
COMMAND
Must be Hi-Z before
the Write Command
CAS latency = 1
DOUT A
DOUT A
DOUT A
DIN A
0
DIN A
DIN A
DIN A
3
0
1
2
1
2
tCK1, DQs
CAS latency = 2
DOUT A
DOUT A
DIN A
DIN A
DIN A
DIN A
3
0
1
0
1
2
t
CK2, DQs
CAS latency = 3
DOUT A
DIN A
DIN A
DIN A
DIN A
3
0
0
1
2
tCK3, DQs
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Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Page 17 of 120
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