Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Read Interrupted by a Read
A Burst Read may be interrupted before completion of the burst by another Read Command, with the only
restriction being that the interval that separates the commands must be at least one clock cycle. When a
burst read operation is interrupted, the remaining addresses of the current burst cycle are overridden starting
with the new column address applied with the interrupting Read Command. The data from the first Read
Command continues to appear on the DQs until the CAS latency of the interrupting Read Command is satis-
fied. At this point, the data from the interrupting Read Command will appear on the DQs and continue for the
full burst length.
Read Interrupted by a Read (Burst Length = 4, CAS Latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ A
READ B
DOUT A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 1
DOUT B
DOUT A
DOUT B
DOUT B
DOUT B
3
0
0
1
2
t
CK1, DQs
CAS latency = 2
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
0
0
1
2
3
t
CK2, DQs
CAS latency = 3
DOUT A
DOUT B
DOUT B
3
0
0
1
2
t
CK3, DQs
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Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Page 16 of 120
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