Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Burst Write Command
The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising
edge of the clock. The address inputs determine the starting column address. There is no CAS latency
required for burst write cycles. Data for the first burst write cycle must be applied on the DQ pins on the same
clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subse-
quent rising clock edge until the burst length is completed. When the burst has finished, any additional data
supplied to the DQ pins will be ignored.
Burst Write Operation (Burst Length = 4, CAS Latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DQs
DIN A
0
don’t care
DIN A
DIN A
DIN A
3
1
2
The first data element and the Write
are registered on the same clock edge.
Extra data is masked.
Write Interrupted by a Write
A burst write operation may be interrupted before completion of the burst. When a burst write cycle is inter-
rupted by a new Write Command, the remaining addresses of the initial write cycle are overridden starting
with the new column address applied with the interrupting Write Command. Data will be written into the
device until the programmed burst length of the last write command is satisfied.
Write Interrupted by a Write (Burst Length = 4, CAS Latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
WRITE A
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DQs
1 Clk Interval
DIN A
DIN B
0
DIN B
DIN B
DIN B
3
0
1
2
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Page 18 of 120
IBM [ IBM ]
