Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Burst Stop Command
Once a burst read or write operation has been initiated, there exist several methods in which to terminate the
burst operation prematurely. These methods include using another Read or Write Command to interrupt an
existing burst operation, using a Precharge Command to interrupt a burst cycle and close the active bank, or
using the Burst Stop Command to terminate the existing burst operation but leave the bank open for future
Read or Write Commands to the same page of the active bank. When interrupting a burst with another Read
or Write Command care must be taken to avoid DQ contention. The Burst Stop Command, however, has the
fewest restrictions making it the easiest method to use when terminating a burst operation before it has been
completed.
The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of
the clock. When using the Burst Stop Command during a burst read cycle, the data DQs go to a high imped-
ance state after a delay which is equal to the CAS Latency set in the Mode Register.
Termination of a Burst Read Operation (Burst Length > 4, CAS Latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Burst
Stop
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
The burst ends after a delay equal to the CAS latency.
The bank remains activated.
CAS latency = 1
DOUT A
DOUT A
DOUT A
DOUT A
DOUT A
DOUT A
DOUT A
0
1
0
2
3
2
1
t
CK1, DQs
CAS latency = 2
DOUT A
DOUT A
DOUT A
3
1
0
t
CK2, DQs
CAS latency = 3
DOUT A
DOUT A
3
2
t
CK3, DQs
When a Burst Stop Command is issued during a burst write operation, only data presented prior to the Burst
Stop command will be written into the device. Any data presented to the device coincident with the Burst Stop
command or later will be ignored.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Page 20 of 120
IBM [ IBM ]
