Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS
high and CAS low at the clock’s rising edge after the necessary RAS to CAS delay (tRCD). WE must also be
defined at this time to determine whether the access cycle is a read operation (WE high), or a write operation
(WE low).
The SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a
serial read or write operation on successive clock cycles at data rates of up to 125 MHz. The number of serial
data bits for each access is equal to the burst length, which is programmed into the Mode Register. Although
the burst length is user programmable, the boundary of the burst cycle is restricted to specific segments of
the page length.
For example, the 2Mbit x 4 I/O x 2 Bank device has a page length of 1024 bits (defined by CA0-CA9). If a
burst length of 4 is programmed into the Mode Register, then the page length is divided into 256 uniquely
addressable boundary segments (4-bits each). A 4-bit burst operation will occur entirely from one of the 256
groups beginning with the column address supplied to the device during the Read or Write Command (CA0-
CA9). The second, third, and fourth access will also occur within this group segment, however, the burst
order is a function of the starting address, the burst sequence, and burst boundary.
The above discussion does not apply when full page burst is programmed into the Mode Register. Full page
burst operation is only allowed for the sequential burst sequence and has no address boundaries. The
SDRAM device will continue bursting data even after all locations of the page have been accessed. The burst
sequence will start at the column address defined during the read or write cycle and will increment sequen-
tially until the highest order column address has been reached. At this point, the burst counter will reset to
address 0 and continue to perform burst read or burst write operations sequentially until either a Burst Stop
Command is issued, a Precharge Command is issued to the bursting bank, or until a new Read or Write
Command is issued.
Similar to Page Mode of conventional DRAMs, a read or write cycle can not begin until the sense amplifiers
latch the selected row address information. The refresh period (tREF) is what limits the number of random col-
umn accesses to an activated bank. A new burst access can be done even before the previous burst ends.
The ability to interrupt a burst operation at every clock cycle is supported, this is referred to as the 1-N rule.
When the previous burst is interrupted by another Read or Write Command, the remaining addresses are
overridden by the new address once the CAS Latency has been satisfied.
Precharging an active bank after each read or write operation is not necessary providing the same row is to
be accessed again. To perform a read or write cycle to a different row within an activated bank, the bank must
be precharged and a new Bank Activate command must be issued. When both Bank A and Bank B are acti-
vated, interleaved (ping pong) bank Read or Write operations are possible. By using the programmed burst
length and alternating the access and precharge operations between the two banks, fast and seamless data
access operation among many different pages can be realized. When the two banks are activated, column to
column interleave operation can be done between two different pages. Finally, Read or Write Commands can
be issued to the same bank or between active banks on every clock cycle.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
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