Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is
registered. The DQs must be in the high impedance state at least one cycle before the interrupting read data
appears on the outputs to avoid data contention. When the Read Command is registered, any residual data
from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Read Command is
initiated will actually be written to the memory.
Write Interrupted by a Read (Burst Length = 4, CAS Latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 1
DIN A
0
DOUT B
0
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
1
2
3
t
CK1, DQs
CAS latency = 2
don’t care
don’t care
DIN A
0
DOUT B
DOUT B
0
1
2
3
t
CK2, DQs
CAS latency = 3
don’t care
DIN A
0
DOUT B
DOUT B
DOUT B
3
0
1
2
t
CK3, DQs
Input data must be removed from the DQs at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
Input data for the Write is masked.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Page 19 of 120
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