IBM0316409C IBM0316809C
IBM0316169C
16Mbit Synchronous DRAM
Automatic Refresh Command (CAS Before RAS Refresh)
When CS, RAS and CAS are held low with CKE and WE high at the rising edge of the clock, the chip enters
the Automatic Refresh mode (CBR). Both banks of the SDRAM must be precharged and idle for a minimum
of the Precharge time (tRP) before the Auto Refresh Command (CBR) can be applied. An address counter,
internal to the device, decrements the word and bank address during the refresh cycle. No control of the
external address pins is required once this cycle has started. The Auto Refresh cycle restores the word line
after the sense amplifiers are set, this eliminates the need to externally apply a Precharge Command.
When the refresh cycle has completed, both banks of the SDRAM will be in the precharged (idle) state. A
delay between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto
Refresh Command must be greater than or equal to the RAS cycle time (tRC).
Self Refresh Command
The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command
is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. Once the
Command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM
has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is
internally disabled during Self Refresh Operation to save power. The user may halt the external clock while
the device is in Self Refresh mode, however, the clock must be restarted before the device can exit Self
Refresh operation. Once the clock is cycling, the device will exit Self Refresh operation on the second posi-
tive clock transition after CKE is returned high. A minimum delay time is required when the device exits Self
Refresh Operation and before the next command can be issued. This delay is equal to the RAS cycle time
(tRC).
Data Mask
The SDRAM has a Data Mask function that can be used in conjunction with data read and write cycles. When
the Data Mask is activated (DQM high) during a write cycle, the write operation is prohibited immediately
(zero clock latency). If the Data Mask is activated during a read cycle, the data outputs are disabled and
become high impedance after a two clock delay, independent of CAS latency.
Data Mask Activated During a Read Cycle (Burst Length = 4, CAS latency = 1)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
NOP
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DOUT A
DQ’s
DOUT A
1
0
A two clock delay before
the DQ’s become Hi-Z
: “H” or “L”
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
07H3997
SA14-4711-02
Revised 05/96
Page 21 of 100
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