IBM0316809C IBM0316409C
IBM0316169C
16Mbit Synchronous DRAM
Command Truth Table (Notes: 1)
CKE
Function
CS
RAS
CAS
WE
DQM A11
A10
A9 - A0
Notes
Previous Current
Cycle
Cycle
Mode Register Set
Auto (CBR) Refresh
Entry Self Refresh
Single Bank Precharge
Precharge all Banks
Bank Activate
H
X
L
L
L
L
L
L
L
L
L
L
L
L
H
X
X
X
H
H
L
L
L
L
L
H
H
L
X
OP Code
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
L
X
X
X
X
H
L
L
H
X
L
H
H
H
L
2
BS
X
H
X
L
L
H
H
X
L
H
L
BS
BS
BS
BS
BS
X
Row Address
2
2
2
2
2
3
Write
H
X
H
H
H
H
H
H
X
X
X
X
X
X
L
H
L
Column
Write with Auto-Precharge
Read
H
X
L
L
Column
H
X
L
H
H
L
Column
Read with Auto-Precharge
Burst Termination
H
X
L
H
X
X
X
X
X
X
X
X
Column
H
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
No Operation
H
X
H
X
X
X
X
X
X
X
Device Deselect
H
X
X
Clock Suspend/Standby Mode
Data Write/Output Enable
Data Mask/Output Disable
Power Down Mode Entry
Power Down Mode Exit
L
X
X
4
5
5
6
6
H
X
X
H
X
H
X
X
X
X
L
X
X
H
X
1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock.
2. Bank Select (BS), if BS = 0 then bank A is selected, if BS = 1 then bank B is selected.
3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4. During normal access mode, CKE is held high and CLK is enabled. When it is low, it freezes the internal clock and extends data
Read and Write operations. One clock delay is required for mode entry and exit.
5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock tim-
ing the data outputs are disabled and become high impedance after a two clock delay. DQM also provides a data mask function for
Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency).
6. All banks must be precharged before entering the Power Down Mode. The Power Down Mode does not preform any refresh oper-
ations, therefore the device can’t remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is
required for mode entry and exit.
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
07H3997
SA14-4711-02
Revised 05/96
Page 24 of 100
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