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IBM0316809CT3-11 参数 Datasheet PDF下载

IBM0316809CT3-11图片预览
型号: IBM0316809CT3-11
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 2MX8, 10ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 100 页 / 1216 K
品牌: IBM [ IBM ]
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IBM0316809C IBM0316409C  
IBM0316169C  
16Mbit Synchronous DRAM  
Burst Stop Command  
Once a burst read or write operation has been initiated, there exist several methods in which to terminate the  
burst operation prematurely. These methods include using another Read or Write Command to interrupt an  
existing burst operation, use a Precharge Command to interrupt a burst cycle and close the active bank, or  
using the Burst Stop Command to terminate the existing burst operation but leave the bank open for future  
Read or Write Commands to the same page of the active bank. When interrupting a burst with another Read  
or Write Command care must be taken to avoid DQ contention. The Burst Stop Command, however, has the  
fewest restrictions making it the easiest method to use when terminating a burst operation before it has been  
completed. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the ris-  
ing edge of the clock.  
When using the Burst Stop Command during a burst read cycle, the data DQ’s go to a high impedance state  
after a delay which is equal to the CAS Latency set in the Mode Register.  
Termination of a Burst Read Operation (Burst Length > 4, CAS latency = 1, 2, 3)  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
Burst  
Stop  
READ A  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
COMMAND  
The burst ends after a delay equal to the CAS latency.  
CAS latency = 1  
DOUT A  
DOUT A  
DOUT A  
DOUT A  
DOUT A  
DOUT A  
DOUT A  
0
1
0
2
3
2
1
t
CK1, DQ’s  
CAS latency = 2  
DOUT A  
DOUT A  
DOUT A  
3
1
0
t
CK2, DQ’s  
CAS latency = 3  
DOUT A  
DOUT A  
3
2
t
CK3, DQ’s  
If a Burst Stop Command is issued during a burst write operation, then any residual data from the burst write  
cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will  
be written to the memory.  
Termination of a Burst Write Operation (Burst Length =X, CAS latency = 1,2,3)  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
Burst  
Stop  
NOP  
WRITE A  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
COMMAND  
CAS latency = 1,2,3  
don’t care  
DIN A  
0
DIN A  
DIN A  
2
1
DQ’s  
Input data for the Write is masked.  
©IBM Corporation, 1996. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
07H3997  
SA14-4711-02  
Revised 05/96  
Page 18 of 100  
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