IBM0316409C IBM0316809C
IBM0316169C
16Mbit Synchronous DRAM
Clock Enable (CKE) Truth Table
CKE
Command
WE
Current State
Action
Notes
Previous Current
CS
RAS CAS
A11 A10 - A0
Cycle
H
L
Cycle
X
X
H
L
X
X
H
H
H
L
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
1
2
2
2
2
2
H
H
H
H
H
L
X
H
H
L
Exit Self Refresh with Device Deselect
Exit Self Refresh with No Operation
ILLEGAL
L
L
L
Self Refresh
L
L
X
X
X
X
X
X
X
X
X
X
H
L
ILLEGAL
L
L
X
X
X
X
X
X
X
X
H
L
ILLEGAL
L
X
X
H
L
X
X
X
X
X
X
H
L
Maintain Self Refresh
INVALID
H
L
X
1
2
2
H
H
L
Power Down mode exit, all banks idle
ILLEGAL
Power Down
L
L
X
H
L
Maintain Power Down Mode
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
3
3
3
Refer to the Idle State section of the
Current State Truth Table
L
L
L
X
X
CBR Refresh
L
L
L
OP Code
Mode Register Set
4
3
3
3
4
All Banks Idle
H
L
X
H
L
X
X
H
L
X
X
X
H
L
Refer to the Idle State section of the
Current State Truth Table
L
L
L
L
L
L
X
X
Entry Self Refresh
Mode Register Set
Power Down
L
L
L
L
OP Code
X
X
X
X
X
X
X
X
4
5
Refer to operations in the Current
State Truth Table
H
H
X
X
X
X
X
Any State
other than
listed above
H
L
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clock Suspend
1. For the given Current State CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for
CKE (tCKS) must be satisfied before any command other than Exit is issued.
3. The address inputs (A11 - A0) depend on the command that is issued. See the Idle State section of the Current State Truth Table
for more information.
4. The Power Down Mode, Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state.
5. Must be a legal command as defined in the Current State Truth Table.
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
07H3997
SA14-4711-02
Revised 05/96
Page 25 of 100
IBM [ IBM ]
