IBM0316409C IBM0316809C
IBM0316169C
16Mbit Synchronous DRAM
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is
registered. The DQ’s must be in the high impedance state at least one cycle before the interrupting read data
appears on the outputs to avoid data contention. When the Read Command is registered, any residual data
from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Read Command is
initiated will actually be written to the memory.
(Burst Length = 4, CAS latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 1
DIN A
0
DOUT B
0
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
1
2
3
t
CK1, DQ’s
CAS latency = 2
don’t care
don’t care
DIN A
0
DOUT B
DOUT B
0
1
2
3
t
CK2, DQ’s
CAS latency = 3
don’t care
DIN A
0
DOUT B
DOUT B
DOUT B
3
0
1
2
t
CK3, DQ’s
Input data must be removed from the DQ’s at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
Input data for the Write is masked.
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
07H3997
SA14-4711-02
Revised 05/96
Page 17 of 100
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