IBM0316409C IBM0316809C
IBM0316169C
16Mbit Synchronous DRAM
Clock Suspend Mode
During normal access mode, CKE is held high enabling the clock. When CKE is registered low while at least
one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the inter-
nal clock and suspends or “freezes” any clocked operation that was currently being executed. There is a one
clock delay between the registration of CKE low and the time at which the SDRAM’s operation suspends.
While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend
mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when
Clock Suspend mode is exited.
When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last
valid data output onto the DQ pins will be actively held valid until Clock Suspend mode is exited.
Clock Suspend During a Read Cycle (Burst Length = 4, CAS latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
CKE
A one clock delay to exit
the Suspend command
A one clock delay before
suspend operation starts
NOP
READ A
NOP
NOP
NOP
NOP
COMMAND
DOUT A
DOUT A
2
DOUT A
DQ0 - DQ3
0
1
: “H” or “L”
DOUT element at the DQ’s when the
suspend operation starts is held valid
If Clock Suspend mode is initiated during a burst write operation, then the input data is masked and ignored
until the Clock Suspend mode is exited.
Clock Suspend During a Write Cycle (Burst Length = 4, CAS latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
CKE
A one clock delay to exit
the Suspend command
A one clock delay before
suspend operation starts
NOP
WRITE A
NOP
NOP
NOP
NOP
COMMAND
DIN A
DIN A
DIN A
3
DIN A
0
DQ0 - DQ3
1
2
: “H” or “L”
DIN is masked during the Clock Suspend Period
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
07H3997
SA14-4711-02
Revised 05/96
Page 23 of 100
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