IBM0316809C IBM0316409C
IBM0316169C
16Mbit Synchronous DRAM
Burst Write with Auto-Precharge (Burst Length = 2, CAS latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
BANK A
ACTIVE
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Auto-Precharge
tDAL
CAS latency = 1
t
CK1, DQ’s
DOUT A
DOUT A
DOUT A
DOUT A
0
1
*
tDAL
CAS latency = 2
t
CK2, DQ’s
0
1
*
tDAL
CAS latency = 3
t
CK3, DQ’s
DOUT A
DOUT A
1
0
*
Begin Autoprecharge
*
Bank can be reactivated at completion of t
DAL
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Com-
mand is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Pre-
charge Command can be used to precharge each bank separately or both banks simultaneously. Two
address bits A10 and A11 (BS) are used to define which bank(s) is to be precharged when the command is
issued.
Bank Selection for Precharge by Address Bits
A10
LOW
LOW
HIGH
BS(A11)
LOW
Precharged Bank(s)
Bank A only
HIGH
Bank B only
DON’T CARE
Both Banks A and B
For read cycles when CAS latency = 1, the Precharge Command may be applied coincident with the last
clock of the burst read cycle. For Read cycles when CAS latency = 2 or 3, the Precharge Command may be
applied coincident with the second to last clock of the burst read cycle.
For write cycles, however, a delay must be satisfied from the start of the last burst write cycle until the Pre-
charge Command can be issued. This delay is known as tDPL, Data-in to Precharge delay.
After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write
access can be executed. The delay between the Precharge Command and the Activate Command must be
greater than or equal to the Precharge time (tRP).
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
07H3997
SA14-4711-02
Revised 05/96
Page 20 of 100
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