1HY5PS12421B(L)FP
1HY5PS12821B(L)FP
1HY5PS121621B(L)FP
-Continue-
DDR2-400
DDR2-533
Symbol
Unit
Note
Parameter
min
max
min
WR+tRP
7.5
max
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
tDAL
WR+tRP
10
-
-
-
-
tCK
ns
14
24
3
tWTR
tRTP
7.5
7.5
ns
tXSNR
tXSRD
tRFC + 10
200
tRFC + 10
200
ns
-
-
-
-
tCK
Exit precharge power down to any non-read
command
tXP
2
2
2
2
tCK
tCK
tCK
Exit active power down to read command
tXARD
tXARDS
1
Exit active power down to read command
(Slow exit, Lower power)
6 - AL
6 - AL
1, 2
CKE minimum pulse width
(high and low pulse width)
t
3
3
tCK
27
16
CKE
t
ODT turn-on delay
ODT turn-on
2
2
2
2
tCK
ns
AOND
t
tAC(min)
tAC(max)+1
tAC(min)
tAC(max)+1
AON
2tCK+
2tCK+
t
ODT turn-on(Power-Down mode)
ODT turn-off delay
tAC(min)+2
2.5
tAC(min)+2
2.5
ns
tCK
ns
AONPD
tAC(max)+1
tAC(max)+1
t
2.5
2.5
AOFD
tAC(max)+
0.6
tAC(max)+
0.6
t
ODT turn-off
tAC(min)
tAC(min)
17
AOF
2.5tCK+
tAC(max)+1
2.5tCK+
tAC(max)+1
t
ODT turn-off (Power-Down mode)
tAC(min)+2
tAC(min)+2
ns
AOFPD
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
tCK
tCK
ns
12
12
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tDelay
tIS+tCK+tIH
tIS+tCK+tIH
ns
15
Rev. 0.7 / Oct. 2007
22
HYNIX [ HYNIX SEMICONDUCTOR ]
