1HY5PS12421B(L)FP
1HY5PS12821B(L)FP
1HY5PS121621B(L)FP
For purposes of IDD testing, the following parameters are to be utilized
Speed
Bin
(CL-tRCD-tRP)
DDR2-800
DDR2-667
DDR2-533
DDR2-400
Units
5-5-5
6-6-6
6
4-4-4
5-5-5
5
3-3-3
4-4-4
4
3-3-3
3
CL(IDD)
5
4
3
tCK
t
12.5
15
12
15
11.25
15
15
RCD(IDD)
ns
ns
t
57.25
7.5
60
57
60
56.25
7.5
60
55
RC(IDD)
t
ns
ns
RRD(IDD)-x4/x8
7.5
7.5
7.5
7.5
7.5
t
RRD(IDD)-x16
10
10
10
3
10
3
10
10
10
5
t
2.5
2.5
3.75
3.75
CK(IDD)
ns
ns
t
45
70000
12.5
75
45
70000
15
45
70000
12
45
70000
15
45
70000
11.25
75
45
70000
15
40
70000
15
RASmin(IDD)
t
ns
ns
ns
RASmax(IDD)
t
RP(IDD)
t
t
75
75
75
75
75
RFC(IDD)-
256Mb
105
105
105
105
105
105
105
ns
ns
RFC(IDD)-
512Mb
t
127.5
127.5
127.5
127.5
127.5
127.5
127.5
RFC(IDD)-1Gb
Detailed IDD7
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the
specification.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
t
t
All banks are being interleaved at minimum RC(IDD) without violating RRD(IDD) using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTs. IOUT = 0mA
Timing Patterns for 4 bank devices x4/ x8/ x16
-DDR2-400 3/3/3: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks)
-DDR2-533 3/3/3: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks)
-DDR2-533 4/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D (16 clocks)
-DDR2-667 4/4/4: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks)
-DDR2-667 5/5/5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks)
Rev. 0.7 / Oct. 2007
19
HYNIX [ HYNIX SEMICONDUCTOR ]
