1HY5PS12421B(L)FP
1HY5PS12821B(L)FP
1HY5PS121621B(L)FP
Timing Parameters by Speed Grade
(Refer to notes for information related to this table at the following pages of this table)
DDR2-400
DDR2-533
Symbol
Unit
Note
Parameter
min
max
min
max
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
-600
-500
0.45
0.45
min(tCL,tCH)
5000
150
+600
-500
-450
0.45
0.45
min(tCL,tCH)
3750
100
+500
ps
ps
tDQSCK
tCH
+500
+450
0.55
0.55
tCK
tCK
ps
CK low-level width
tCL
0.55
0.55
CK half period
tHP
-
-
11,12
15
Clock cycle time, CL=x
tCK
8000
8000
ps
DQ and DM input setup time(differential strobe)
DQ and DM input hold time(differential strobe)
DQ and DM input setup time(single ended strobe)
DQ and DM input hold time(single ended strobe)
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
tDS(base)
tDH(base)
tDS
-
-
ps
6,7,8,20
6,7,8,21
6,7,8,20
6,7,8,21
275
-
225
-
ps
25
-
-25
-
ps
tDH
25
-
-25
-
ps
tIPW
0.6
-
0.6
-
tCK
tCK
ps
tDIPW
tHZ
0.35
-
-
0.35
-
-
tAC max
tAC max
18
18
18
13
12
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tAC min
2*tAC min
-
tAC max
tAC min
2*tAC min
-
tAC max
ps
tAC max
tAC max
ps
350
300
ps
-
450
-
400
ps
DQ/DQS output hold time from DQS
First DQS latching transition to associated clock edge
DQS input high pulse width
tQH
tHP - tQHS
-0.25
0.35
0.35
0.2
-
tHP - tQHS
-0.25
0.35
0.35
0.2
-
ps
tDQSS
tDQSH
tDQSL
tDSS
+ 0.25
+ 0.25
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
-
-
DQS input low pulse width
-
-
-
-
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDSH
0.2
-
0.2
-
tMRD
2
-
2
-
tWPST
tWPRE
tIS(base)
tIH(base)
tRPRE
tRPST
0.4
0.6
-
0.4
0.6
-
10
Write preamble
0.35
350
0.35
250
Address and control input setup time
Address and control input hold time
Read preamble
-
-
5,7,9,23
5,7,9,23
475
-
375
-
ps
0.9
1.1
0.6
0.9
1.1
0.6
tCK
tCK
Read postamble
0.4
0.4
Active to active command period for 1KB page size
products
tRRD
tRRD
7.5
10
-
-
7.5
10
-
-
ns
ns
4
4
Active to active command period for 2KB page size
products
Four Active Window for 1KB page size products
Four Active Window for 2KB page size products
CAS to CAS command delay
tFAW
tFAW
tCCD
tWR
37.5
50
2
-
-
37.5
50
2
-
-
ns
ns
tCK
ns
Write recovery time
15
-
15
-
Rev. 0.7 / Oct. 2007
21
HYNIX [ HYNIX SEMICONDUCTOR ]
