1HY5PS12421B(L)FP
1HY5PS12821B(L)FP
1HY5PS121621B(L)FP
VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its comple-
ment, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differen-
tial data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a
20 ohm to 10 K ohm resistor to insure proper operation.
t
t
DQSL
DQSH
DQS
DQS
DQS/
DQS
t
t
WPST
WPRE
V
(dc)
V
(ac)
IH
IH
DQ
DM
D
D
D
t
D
t
V
(ac)
V
(dc)
IL
IL
t
t
DS
DH
DH
DS
V
(dc)
V
(ac)
IH
IH
DMin
DMin
DMin
(ac)
DMin
V
IL
V
(dc)
IL
Figure -- Data input (write) timing
t
t
CL
CH
CK
CK
CK/CK
DQS
DQS
DQS/DQS
DQ
t
t
RPRE
RPST
Q
Q
Q
Q
t
DQSQmax
t
DQSQmax
t
t
QH
QH
Figure -- Data output (read) timing
5. AC timings are for linear signal transitions. See System Derating for other signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device.
They may be guaranteed by device design or tester correlation.
7. All voltages referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/
supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage
range specified.
Rev. 0.7 / Oct. 2007
26
HYNIX [ HYNIX SEMICONDUCTOR ]
