1HY5PS12421B(L)FP
1HY5PS12821B(L)FP
1HY5PS121621B(L)FP
DDR2-667
min
DDR2-800
Symbol
Unit
Note
Parameter
max
+450
+400
0.55
min
-400
-350
0.45
0.45
max
+400
+350
0.55
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
-450
-400
0.45
0.45
ps
ps
tDQSCK
tCH
tCK
tCK
CK low-level width
tCL
0.55
0.55
min(tCL,
tCH)
min(tCL,
tCH)
CK half period
tHP
-
-
ps
11,12
Clock cycle time, CL=x
tCK
3000
8000
2500
ps
ps
15
DQ and DM input setup time
DQ and DM input hold time
tDS(base)
tDH(base)
100
-
50
-
6,7,8,20
6,7,8,21
175
-
125
-
ps
Control & Address input pulse width for each input tIPW
0.6
-
-
0.6
-
-
tCK
tCK
ps
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
tDIPW
tHZ
0.35
0.35
-
tAC max
tAC max
tAC max
240
-
tAC max
tAC max
tAC max
200
18
18
18
13
12
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tAC min
tAC min
ps
2*tAC min
2*tAC min
ps
-
-
ps
-
340
-
300
ps
DQ/DQS output hold time from DQS
tQH
tHP - tQHS
-
tHP - tQHS
-
ps
First DQS latching transition to associated clock
edge
tDQSS
- 0.25
+ 0.25
- 0.25
+ 0.25
tCK
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
0.2
2
-
0.35
0.35
0.2
0.2
2
-
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
-
-
-
-
tDSH
-
-
tMRD
-
0.6
-
-
0.6
-
tWPST
tWPRE
tIS(base)
tIH(base)
tRPRE
tRPST
tRAS
0.4
0.35
200
275
0.9
0.4
45
0.4
0.35
175
250
0.9
0.4
45
10
Write preamble
Address and control input setup time
Address and control input hold time
Read preamble
-
-
5,7,9,22
-
-
ps
5,7,9,23
1.1
0.6
70000
1.1
0.6
70000
tCK
tCK
ns
19
19
3
Read postamble
Activate to precharge command
Active to active command period for 1KB page size
products
tRRD
tRRD
7.5
10
-
-
7.5
10
-
-
ns
ns
4
4
Active to active command period for 2KB page size
products
Four Active Window for 1KB page size products
Four Active Window for 2KB page size products
CAS to CAS command delay
tFAW
tFAW
tCCD
tWR
37.5
-
-
37.5
-
-
ns
ns
50
2
50
2
tCK
ns
Write recovery time
15
-
-
15
-
-
Auto precharge write recovery + precharge time
tDAL
WR+tRP
WR+tRP
tCK
14
Rev. 0.7 / Oct. 2007
23
HYNIX [ HYNIX SEMICONDUCTOR ]
