11
1Gbit (32Mx32bit) Mobile SDR Memory
H55S1G(2/3)2MFP Series
WRITE to READ
CLK
Command
WRITE
READ
BA, Col
b
BA, Col
n
Address
CL = 2
CL = 3
BL = 4
BL = 4
D
I
b1
DOn0
D
I
b0
DOn1
DOn0
DOn2 DOn3
DQ
DQ
DIb1
DIb0
DOn1
DOn2
DOn3
Don't Care
The preceding burst write operation can be aborted and a new burst read operation can be started by inputting a new
read command in the write cycle. The data of the read command (READ) is output after the lapse of the /CAS latency.
The preceding write operation (WRIT) writes only the data input before the read command.
The data bus must go into a high-impedance state at least one cycle before output of the latest data.
Notes:
1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank
as the preceding write command, the read command can be performed after an interval of no less than 1 clock.
However, in the case of a burst write, data will continue to be written until one clock before the read command is
executed.
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be
executed; it is necessary to separate the two commands with a precharge command and a bank active command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. However, in the case of a burst write, data will
continue to be written until one clock before the read command is executed (as in the case of the same bank
and the same address).
Rev 1.2 / Jun. 2008
36
HYNIX [ HYNIX SEMICONDUCTOR ]
