11
1Gbit (32Mx32bit) Mobile SDR Memory
H55S1G(2/3)2MFP Series
WRITE to PRECHARGE
Data for any WRITE burst may be followed by a subsequent PRECHARGE command to the same bank (provided Auto
Precharge was not activated). When the precharge command is executed for the same bank as the write command
that preceded it, the minimum interval between the two commands is 1 clock. However, if the burst write operation is
unfinished, the input data must be masked by means of DQM for assurance of the clock defined by tDPL. To follow a
WRITE without truncating the WRITE burst, tDPL should be met as shown in Fig.
CLK
Command
Address
WRITE
PRE
BA, Col
b
CL = 2 or 3
BL = 4
DIb0
DIb3
DIb1
DIOb2
DQ
tDPL
Non-Interrupting Write to Precharge
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command as shown in Figure.
Note that only data-inthat are registered prior to the tDPL period are written to the internal array, and any subsequent
data-in should be masked with DM, as shown in next Fig. Following the PRECHARGE command, a subsequent com-
mand to the same bank cannot be issued until tRP is met.
CLK
Command
Address
WRITE
PRE
BA, Col
b
CL = 2 or 3
BL = 4
DIb0
DIb1
DIOb2
tDPL
DQ
Interrupting Write to Precharge
Rev 1.2 / Jun. 2008
37
HYNIX [ HYNIX SEMICONDUCTOR ]
