11
1Gbit (32Mx32bit) Mobile SDR Memory
H55S1G(2/3)2MFP Series
Write
Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing
coincident with the data. If a given DM signal is registered Low, the corresponding data will be written to the memory;
if the DM signal is registered High, the corresponding data inputs will be ignored, and a write will not be executed to
that byte / column location.
During WRITE bursts, the first valild data-in element will be registered coincident with the WRITE command. Subse-
quent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length
burst, assuming no other commands have been initiated, the DQ will remain High-Z and any additional input data will
be ignored. A full-page burst will continue until terminated.
Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE
burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any
clock following the previous WRITE command, and the data provided coincident with the new command applies to the
new command.
CLK
Command
Address
WRITE
BA, Col
b
DQ
DQ
BL = 1
BL = 2
BL = 4
BL = 8
DIb0
DIb1
DIb1
D
I
b0
DIb0
b0
DQ
DQ
DIb2
b2
DIb3
b3
D
I
b1
DIb4
D
I
DIb5
D
I
D
I
DIb6
DIb7
Don't Care
CL = 2 or 3
Basic Write timing parameters for Write Burst Operation
Notes :
1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the
preceding write command, the second write can be performed after an interval of no less than 1 clock. In the case of burst writes,
the second write command has priority.
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed;
it is necessary to separate the two write commands with a precharge command and a bank active command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 clock,
provided that the other bank is in the bank active state. In the case of burst write, the second write command has priority.
Rev 1.2 / Jun. 2008
34
HYNIX [ HYNIX SEMICONDUCTOR ]
