APCPCWM_4828539:WP_0000001WP_0000001
1
H27(U_S)4G8_6F2D
4 Gbit (512M x 8 bit) NAND Flash
ADDR ADDR ADDR
Cꢂcꢄe Tꢂpe
ADDR ADDR
DIN
ꢈꢈꢈ
CMD
11ꢇ
CMD
82ꢇ
DIN
DIN
DIN
tADL
C1
A
C±
A
DnA
R±
A
R3
A
D2
A
D1A
R1
A
DQx
tADL
tIPBSY
SR[6]
A
Cꢂcꢄe Tꢂpe
DQx
DIN
ꢈꢈꢈ
ADDR ADDR ADDR
DIN
DIN
DIN
CMD
12ꢇ
ADDR ADDR
CMD
82ꢇ
tADL
Dn
B
D2
B
D1BA
C1
B
C±
B
R1B
R±
B
R3B
tADL
tPROG
SR[6]
Figure 21 : Multiple plane page program (ONFI 1.0 protocol)
NOTES :
C1A-C2A Column address for page A. C1A is the least significant byte.
R1A-R3A Row address for page A. R1A is the least significant byte.
D0A-DnA Data to program for page A.
C1B-C2B Column address for page B. C1B is the least significant byte.
R1B-R3B Row address for page B. R1B is the least significant byte.
D0B-DnB Data to program for page B.
Same restrictions on address of pages A and B, and allowed commands as Figure 20 apply
Rev 1.4 / OCT. 2010
43
B34416/177.179.157.84/2010-10-08 10:08
*ba53f20d-240c*
HYNIX [ HYNIX SEMICONDUCTOR ]
