HC6856
FUNCTIONAL DIAGRAM
•
•
•
32,768 x 8
Memory
Array
A:0-8,12-13
CE
Row
Decoder
11
•
•
•
8
Column Decoder
Data Input/Output
NCS
DQ:0-7
8
NWE
WE • CS • CE
1 = enabled
Signal
NWE • CS • CE • OE
(0 = high Z)
NOE
Signal
#
CS • CE
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
A:9-11,14
4
SIGNAL DEFINITIONS
A: 0-14
DQ: 0-7
Address input pins (A) which select a particular eight-bit word within the memory array.
Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
NCS
Negative chip select, when at a low level allows normal read or write operation. When at a high level it forces
the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all
the input buffers. If this signal is not used it must be connected to VSS.
NWE
NOE
Negative write enable, when at a low level activates a write operation and holds the data output drivers in a
high impedance state. When at a high level it allows normal read operation.
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must
be connected to VSS.
CE
Chip enable, when at a high level allows normal operation. When at a low level it forces the SRAM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers.
If this signal is not used it must be connected to VDD.
TRUTH TABLE
NCS
CE
NWE
NOE
MODE
DQ
L
L
H
H
X
L
H
L
L
Read
Write
Data Out
Data In
High Z
Notes:
X: VI=VIH or VIL
X
XX: VSS≤VI≤VDD
NOE=H: High Z output state maintained for
NCS=X, CE=X, NWE=X
H
X
XX
XX
XX
XX
Deselected
Disabled
High Z
2
HONEYWELL [ Honeywell ]
