HT46R01A
:
:
; As the Port A channel bits have changed the
; following START
; signal (0-1-0) must be issued within 10
; instruction cycles
Start_conversion:
clr
set
clr
Polling_EOC:
sz
START
START
START
; reset A/D
; start A/D
EOCB
; poll the ADCR register EOCB bit to detect end
; of A/D conversion
; continue polling
; read conversion result value from the ADR
; register
; save result to user defined memory
jmp
mov
polling_EOC
a,ADR
mov
jmp
adr_buffer,a
:
:
start_conversion
; start next A/D conversion
Example: using an interrupt method to detect the end of conversion
clr
mov
mov
EADI
a,00000001B
ACSR,a
; disable ADC interrupt
; setup the ACSR register to select fSYS/8 as
; the A/D clock
mov
mov
a,00100000B
; setup ADCR register to configure Port PA0~PA3
; as A/D inputs
; and select AN0 to be connected to the A/D
; converter
ADCR,a
:
; As the Port A channel bits have changed the
; following START
; signal (0-1-0) must be issued within 10
; instruction cycles
:
Start_conversion:
clr
set
clr
clr
set
set
START
START
START
ADF
EADI
EMI
:
; reset A/D
; start A/D
; clear ADC interrupt request flag
; enable ADC interrupt
; enable global interrupt
:
:
; ADC interrupt service routine
ADC_ISR:
mov
mov
mov
acc_stack,a
a,STATUS
status_stack,a
:
; save ACC to user defined memory
; save STATUS to user defined memory
:
a,ADR
mov
mov
; read conversion result value from the ADR
; register
; save result to user defined register
adr_buffer,a
:
:
EXIT_INT_ISR:
mov
mov
mov
reti
a,status_stack
STATUS,a
a,acc_stack
; restore STATUS from user defined memory
; restore ACC from user defined memory
Rev. 1.10
29
August 13, 2008
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