HT46R01A
b
7
b
0
E
O
C
B
P
C
R
2
P
C
R
1
P
C
R
0
A
C
S
2
A
C
S
1
A
C
S
0
S
T
A
R
T
A
D
C
R
R
e
g
i
s
t
e
r
S
A
e
C
l
e
c
t
A
/
D
c
h
a
n
n
e
l
S
2
A
C
S
1
A
C
S
0
0
0
0
0
1
0
0
1
1
0
1
0
1
:
:
:
:
:
A
A
A
A
u
N
N
N
N
0
1
2
3
X
X
n
d
e
f
i
n
e
d
,
m
u
s
t
n
o
t
b
e
u
s
e
d
P
o
r
t
B
A
/
D
c
h
a
n
n
e
l
c
o
n
f
i
g
u
r
a
t
i
o
n
s
P
C
R
2
P
C
R
1
P
C
R
0
0
0
0
0
1
0
0
1
1
0
1
0
1
:
P
o
r
t
B
A
/
D
c
h
a
n
n
e
l
s
-
a
l
l
o
f
f
:
P
B
0
e
n
a
b
l
e
d
a
s
A
N
0
:
P
B
0
~
P
B
1
e
n
a
b
l
e
d
a
s
A
N
0
~
A
N
1
:
:
P
P
B
B
0
0
~
~
P
P
B
B
2
3
e
e
n
n
a
a
b
b
l
l
e
e
d
d
a
a
s
s
A
A
N
N
0
0
~
~
A
A
N
N
2
3
X
X
E
1
0
n
d
o
f
A
/
D
c
o
n
v
e
r
s
i
o
n
f
l
a
g
:
n
o
t
e
n
d
o
f
A
/
D
c
o
n
v
e
r
s
i
o
n
-
A
/
D
c
o
n
v
e
r
s
i
o
n
w
a
i
t
i
n
g
o
r
i
n
p
r
o
g
r
e
s
s
:
e
n
d
o
f
A
/
D
c
o
n
v
e
r
s
i
o
n
-
A
/
D
c
o
n
v
e
r
s
i
o
n
e
n
d
e
d
S
t
a
r
t
t
h
e
A
/
D
c
o
n
v
e
r
s
i
o
n
0
0
®
1
®
0
:
S
t
a
r
t
®
1
:
R
e
s
e
t
A
/
D
c
o
n
v
e
r
t
e
r
a
n
d
s
e
t
E
O
C
B
t
o
"
1
"
ADCR Register
b
7
b
0
A
D
C
S
2
D
C
S
1
A
D
C
S
0
T
E
S
T
A
C
S
R
R
e
g
i
s
t
e
r
S
A
e
l
e
c
t
A
/
D
c
o
n
v
e
r
t
e
r
c
l
o
c
k
s
o
u
r
c
e
D
C
S
2
A
D
C
S
1
A
D
C
S
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
:
s
y
s
t
e
m
c
l
o
c
k
/
2
:
s
y
y
s
s
t
t
e
e
m
m
c
c
l
l
o
o
c
c
k
k
/
/
8
3
:
s
2
:
u
n
d
e
f
i
n
e
d
:
:
s
s
y
y
y
s
s
s
t
t
t
e
e
e
m
m
m
c
c
c
l
l
l
o
o
o
c
c
c
k
k
k
/
/
4
1
:
s
6
:
u
n
d
e
f
i
n
e
d
N
F
o
t
i
m
e
p
l
e
m
m
e
n
t
e
u
d
s
,
r
e
a
d
a
s
"
0
"
o
r
t
s
t
o
d
e
e
o
n
l
y
ACSR Register
A/D Clock Period (tAD)/ADCS0~ADCS2
fSYS
fSYS
100
fSYS/2
000
fSYS/4
101
fSYS/8
001
fSYS/16
110
fSYS/32
010
1MHz
2MHz
4MHz
8MHz
1ms
2ms
1ms
4ms
2ms
8ms
4ms
16ms
8ms
32ms
16ms
8ms
500ns*
250ns*
125ns*
83.3ns*
500ns*
250ns*
1ms
2ms
4ms
500ns*
333.3ns*
1ms
2ms
4ms
12MHz
166.7ns*
666.7ns*
1.33ms
2.67ms
A/D Clock Period Examples
Rev. 1.10
26
August 13, 2008
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
