HI-3593
TIMING DIAGRAMS
SERIAL INPUT TIMING DIAGRAM
t CPH
tCYC
CS
tCHH
tCES
t SCKF
t CEH
SCK
tDS
SI
tDH
t SCKR
MSB
LSB
SERIAL OUTPUT TIMING DIAGRAM
t CPH
tCYC
CS
tSCKH
tSCKL
SCK
t CHZ
t DV
SO
MSB
LSB
Hi Impedance
Hi Impedance
DATA RATE - EXAMPLE PATTERN
TXAOUT
ARINC BIT
TXBOUT
DATA
NULL
DATA
DATA
NULL
BIT 32
NULL
BIT 1
NEXT WORD
WORD GAP
BIT 31
BIT 30
RECEIVER OPERATION
BIT 31
BIT 32
ARINC DATA
FLAGS (1)
tINTW
R1INT / R2INT
tRFLG
tSPIF
tRXR
CS
SI
SPI INSTRUCTION (E.g. 0xA0)
ARINC
BIT 32
ARINC
BIT 31
ARINC
BIT 30
ARINC
BIT 1
SO
(1) Receiver status flag outputs: R1FLAG, R2FLAG, MB1-1, MB1-2, MB1-3, MB2-1, MB2-2, MB2-3
HOLT INTEGRATED CIRCUITS
16