Preliminary
Routine) both employ the table read instruc-
tion, the contents of the TBLH in the main
routine are likely to be changed by the table
read instruction used in the ISR. Errors can
occur. In other words, using the table read in-
struction in the main routine and the ISR si-
multaneously should be avoided. However, if
the table read instruction has to be applied in
both the main routine and the ISR, the inter-
rupt is supposed to be disabled prior to the ta-
ble read instruction. It will not be enabled
until the TBLH has been backed up. All table
related instructions require two cycles to com-
plete the operation. These areas may function
as normal program memory depending upon
the requirements.
Stack register
-
STACK
This is a special part of the memory which is
used to save the contents of the program coun-
ter (PC) only. The stack is organized into 2 lev-
els and is neither part of the data nor part of the
program space, and is neither readable nor
writable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt ac-
knowledgment, the contents of the program
counter are pushed onto the stack. At the end of
a subroutine or an interrupt routine, signaled
by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value
from the stack. After a chip reset, the SP will
point to the top of the stack.
If the stack is full and a non-masked interrupt
takes place, the interrupt request flag will be
recorded but the acknowledgment will be inhib-
Instruction
TABRDC [m]
TABRDL [m]
HT48R06A-1
ited. When the stack pointer is decremented (by
RET or RETI), the interrupt will be serviced.
This feature prevents stack overflow allowing
the programmer to use the structure more eas-
ily. In a similar case, if the stack is full and a
"CALL" is subsequently executed, stack over-
flow occurs and the first entry will be lost (only
the most recent 2 return addresses are stored).
Data memory
-
RAM
The data memory is designed with 81´8 bits.
The data memory is divided into two func-
tional groups: special function registers and
general purpose data memory (64´8). Most are
read/write, but some are read only.
The special function registers include the indi-
rect addressing register (00H), timer/event
counter (TMR;0DH), timer/event counter con-
trol register (TMRC;0EH), program counter
lower-order byte register (PCL;06H), memory
pointer register (MP;01H), accumulator
(ACC;05H), table pointer (TBLP;07H), table
higher-order byte register (TBLH;08H), status
register (STATUS;0AH), interrupt control reg-
ister (INTC;0BH), watchdog timer option set-
ting register (WDTS;09H), I/O registers
(PA;12H, PB;14H, PC;16H) and I/O control
registers (PAC;13H, PBC;15H, PCC;17H). The
remaining space before the 40H is reserved for
future expanded usage and reading these loca-
tions will get "00H". The general purpose data
memory, addressed from 40H to 7FH, is used
for data and control information under in-
struction commands.
Table Location
*9
P9
1
*8
P8
1
*7
@7
@7
*6
@6
@6
*5
@5
@5
*4
@4
@4
*3
@3
@3
*2
@2
@2
*1
@1
@1
*0
@0
@0
Table location
Note: *9~*0: Table location bits
@7~@0: Table pointer bits
P9, P8: Current program counter bits
8
February 25, 2000
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
