Preliminary
HT48R06A-1
The states of the registers is summarized in the table.
WDT time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
WDT
Time-out
(HALT)*
Reset
(Power On)
RES Reset
(HALT)
Register
TMR
xxxx xxxx
00-0 1000
uuuu uuuu
00-0 1000
uuuu uuuu
00-0 1000
uuuu uuuu
00-0 1000
uuuu uuuu
uu-u uuuu
TMRC
Program
Counter
000H
000H
000H
000H
000H
MP
-xxx xxxx
xxxx xxxx
xxxx xxxx
--xx xxxx
--00 xxxx
--00 -000
0000 0111
1111 1111
1111 1111
---- -111
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--1u uuuu
--00 -000
0000 0111
1111 1111
1111 1111
---- -111
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--uu uuuu
--00 -000
0000 0111
1111 1111
1111 1111
---- -111
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--01 uuuu
--00 -000
0000 0111
1111 1111
1111 1111
---- -111
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--11 uuuu
--uu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
ACC
TBLP
TBLH
STATUS
INTC
WDTS
PA
PAC
PB
PBC
PC
---- -111
---- -111
---- -111
---- -111
---- -uuu
------11
------11
------11
------11
------uu
PCC
------11
------11
------11
------11
------uu
Note: "*" means "warm reset"
"u" means "unchanged"
"x" means "unknown"
15
February 25, 2000
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
