HT46RU66/HT46CU66
·
7+1 PWM Mode
Parameter
AC (0~1)
Duty Cycle
DC+ 1
128
Each full PWM cycle, as it is controlled by an 8-bit
PWM register, has 256 clock periods. However, in the
7+1 PWM mode, each PWM cycle is subdivided into
two individual sub-cycles known as modulation cycle 0
~ modulation cycle 1, denoted as ²i² in the table. Each
one of these two sub-cycles contains 128 clock cycles.
In this mode, a modulation frequency increase of two is
achieved. The 8-bit PWM register value, which repre-
sents the overall duty cycle of the PWM waveform, is
divided into two groups. The first group which consists
of bit1~bit7 is denoted here as the DC value. The sec-
ond group which consists of bit0 is known as the AC
value. In the 7+1 PWM mode, the duty cycle value of
each of the two modulation sub-cycles is shown in the
following table.
i<AC
Modulation cycle i
(i=0~1)
DC
i³AC
128
7+1 Mode Modulation Cycle Values
The following diagram illustrates the waveforms asso-
ciated with the 7+1 mode PWM operation. It is impor-
tant to note how the single PWM cycle is subdivided
into 2 individual modulation cycles, numbered 0 and 1
and how the AC value is related to the PWM value.
S
Y
S
[
P
W
M
]
=
1
0
0
P
W
M
5
0
/
1
2
8
5
0
/
1
2
8
5
0
/
1
2
8
[
P
W
M
]
=
1
0
1
P
W
M
5
1
/
1
2
8
5
0
/
1
2
8
5
1
/
1
2
8
[
P
W
M
]
=
1
0
2
P
W
M
5
1
/
1
2
8
5
1
/
1
2
8
5
1
/
1
2
8
[
P
W
M
]
=
1
0
3
P
W
M
5
1
/
1
2
8
5
2
/
1
2
8
5
2
/
1
2
8
P
W
M
m
o
d
u
l
a
t
i
o
n
p
e
r
i
o
d
:
1
2
8
/
f
M
o
d
u
l
a
t
i
o
n
c
y
c
l
e
0
M
o
d
u
l
a
t
i
o
n
c
y
c
l
e
1
M
o
d
u
l
a
t
i
o
n
c
y
c
l
e
0
P
W
M
c
y
c
l
e
:
2
5
6
/
f
(7+1) PWM Mode
b
7
b
0
P
W
M
R
e
g
i
s
t
e
r
(
7
+
1
)
M
o
d
e
A
D
C
v
a
l
u
u
e
C
v
a
l
e
PWM Register for 7+1 Mode
·
PWM Output Control
corresponding bit in the PD output data register will en-
able the PWM data to appear on the pin. Writing a ²0²
to the corresponding bit in the PD output data register
will disable the PWM output function and force the out-
put low. In this way, the Port D data output register can
be used as an on/off control for the PWM function. Note
that if the configuration options have selected the PWM
function, but a ²1² has been written to its corresponding
bit in the PDC control register to configure the pin as an
input, then the pin can still function as a normal input
line, with pull-high resistor options.
On all devices, the PWM outputs are pin-shared with
the Port D I/O pins. To operate as PWM outputs and not
as I/O pins, the correct PWM configuration options
must be selected. A ²0² must also be written to the cor-
responding bits in the I/O port control register PDC to
ensure that the required PWM output pins are setup as
outputs. After these two initial steps have been carried
out, and of course after the required PWM value has
been written into the PWM register, writing a ²1² to the
Rev. 1.20
27
October 2, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
