HT46RU66/HT46CU66
For all devices, the PWM clock source is the system clock fSYS
.
Package
52/56-pin
100-pin
Channels
PWM Mode
6+2 or 7+1
6+2 or 7+1
Output Pin
PD0/PD1/PD2
PWM Register Name
PWM0/PWM1/PWM2
3
4
PWM0/PWM1/PWM2/PWM3
PD0/PD1/PD2/PD3
PWM Function Table
four individual sub-cycles known as modulation cycle
0 ~ modulation cycle 3, denoted as ²i² in the table.
Each one of these four sub-cycles contains 64 clock
cycles. In this mode, a modulation frequency increase
of four is achieved. The 8-bit PWM register value,
which represents the overall duty cycle of the PWM
waveform, is divided into two groups. The first group
which consists of bit2~bit7 is denoted here as the DC
value. The second group which consists of bit0~bit1 is
known as the AC value. In the 6+2 PWM mode, the
duty cycle value of each of the four modulation
sub-cycles is shown in the following table.
This method of dividing the original modulation cycle
into a further 2 or 4 sub-cycles enable the generation of
higher PWM frequencies which allow a wider range of
applications to be served. As long as the periods of the
generated PWM pulses are less than the time constants
of the load, the PWM output will be suitable as such long
time constant loads will average out the pulses of the
PWM output. The difference between what is known as
the PWM cycle frequency and the PWM modulation fre-
quency should be understood. As the PWM clock is the
system clock, fSYS, and as the PWM value is 8-bits wide,
the overall PWM cycle frequency is fSYS/256. However,
when in the 7+1 mode of operation the PWM modulation
frequency will be fSYS/128, while the PWM modulation
frequency for the 6+2 mode of operation will be fSYS/64.
Parameter
AC (0~3)
Duty Cycle
DC+ 1
64
i<AC
Modulation cycle i
(i=0~3)
DC
64
i³AC
PWM
PWM Cycle PWM Cycle
Modulation Frequency Frequency
Duty
6+2 Mode Modulation Cycle Values
f
f
SYS/64 for (6+2) bits mode
f
SYS/256
[PWM]/256
SYS/128 for (7+1) bits mode
The following diagram illustrates the waveforms asso-
ciated with the 6+2 mode PWM operation. It is impor-
tant to note how the single PWM cycle is subdivided
into 4 individual modulation cycles, numbered from
0~3 and how the AC value is related to the PWM
value.
·
6+2 PWM Mode
Each full PWM cycle, as it is controlled by an 8-bit
PWM register, has 256 clock periods. However, in the
6+2 PWM mode, each PWM cycle is subdivided into
S
Y
S
[
P
W
M
]
=
1
0
0
P
W
M
2
5
/
6
4
2
2
2
2
5
5
6
6
/
/
/
/
6
6
6
6
4
4
4
4
2
5
/
6
4
2
5
/
6
4
2
2
2
2
5
6
6
6
/
/
/
/
6
6
6
6
4
4
4
4
[
P
W
M
]
=
1
0
1
P
W
M
2
6
/
6
4
2
5
/
6
4
2
5
/
6
4
[
P
W
M
]
=
1
0
2
P
W
M
2
6
/
6
4
2
5
/
6
4
2
5
/
6
4
[
P
W
M
]
=
1
0
3
P
W
M
2
6
/
6
4
2
6
/
6
4
2
5
/
6
4
P
W
M
m
o
d
u
l
a
t
i
o
n
p
e
r
i
o
d
:
6
4
/
f
M
o
d
u
l
a
t
i
o
n
c
y
c
l
e
0
M
o
d
u
l
a
t
i
o
n
c
y
c
l
e
1
M
o
d
u
l
a
t
i
o
n
c
y
c
l
e
2
M
o
d
u
l
a
t
i
o
n
c
y
c
l
e
3
M
o
d
u
l
a
t
i
o
n
c
y
c
l
e
0
P
W
M
c
y
c
l
e
:
2
5
6
/
f
6+2 PWM Mode
b
7
b
0
P
W
M
R
e
g
i
s
t
e
r
(
6
+
2
)
M
o
d
e
A
D
C
v
a
l
u
u
e
C
v
a
l
e
PWM Register for 6+2 Mode
Rev. 1.20
26
October 2, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
