HT46R64/HT46C64
The following programming example illustrates how to setup and implement an A/D conversion. The method of polling
the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete.
Example: using EOCB Polling Method to detect end of conversion
mov
mov
mov
mov
a,00000001B
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
; and select AN0 to be connected to the A/D converter
a,00100000B
ADCR,a
:
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
set
clr
START
START
START
; reset A/D
; start A/D
Polling_EOC:
sz
EOCB
; poll the ADCR register EOCB bit to detect end of A/D conversion
; continue polling
jmp
mov
mov
mov
mov
polling_EOC
a,ADRH
adrh_buffer,a
a,ADRL
; read conversion result high byte value from the ADRH register
; save result to user defined memory
; read conversion result low byte value from the ADRL register
; save result to user defined memory
adrl_buffer,a
:
:
jmp
start_conversion
; start next A/D conversion
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A/D Conversion Timing
Rev. 1.80
24
February 14, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
