HT46R64/HT46C64
Low Voltage Reset/Detector Functions
There is a low voltage detector (LVD) and a low voltage reset circuit (LVR) implemented in the microcontroller. These
two functions can be enabled/disabled by options. Once the LVD options is enabled, the user can use the RTCC.3 to
enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from RTCC.5; otherwise, the LVD function is
disabled.
The RTCC register definitions are listed below.
Bit No.
0~2
3
Label
Function
RT0~RT2 8 to 1 multiplexer control inputs to select the real clock prescaler output
LVDC
LVD enable/disable (1/0)
32768Hz OSC quick start-up oscillating
0/1: quickly/slowly start
4
QOSC
LVD detection output (1/0)
5
LVDO
1: low voltage detected, read only
6~7
¾
Unused bit, read as ²0²
RTCC (09H) Register
The LVR has the same effect or function with the exter-
nal RES signal which performs chip reset. During HALT
state, LVR is disabled both LVR and LVD are disabled.
The relationship between VDD and VLVR is shown below.
V
D
D
V
O P R
5
.
5
V
5
.
5
V
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as changing a battery, the LVR will au-
tomatically reset the device internally.
V
L
V
R
3
.
0
V
2
.
2
V
The LVR includes the following specifications:
·
The low voltage (0.9V~VLVR) has to remain in their
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
0
.
9
V
Note: VOPR is the voltage range for proper chip
operation at 4MHz system clock.
·
The LVR uses the ²OR² function with the external RES
signal to perform chip reset.
V
D
D
5
.
5
V
L
V
R
D
e
t
e
c
t
V
o
l
t
a
g
e
V
L
V
R
0
.
9
0
V
V
R
e
s
e
t
S
i
g
n
a
l
R
e
s
e
t
N
o
r
m
a
l
O
p
e
r
a
t
i
o
n
R
e
s
e
t
*
1
*
2
Low Voltage Reset
Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay,
the device enters the reset mode.
Rev. 1.80
27
February 14, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
