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HT46R47E 参数 Datasheet PDF下载

HT46R47E图片预览
型号: HT46R47E
PDF下载: 下载PDF文件 查看货源
内容描述: 高性价比的A / D型8位MCU [Cost-Effective A/D Type 8-Bit MCU]
分类和应用:
文件页数/大小: 45 页 / 335 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT46R47E/HT46C47E  
Once a wake-up event occurs, it takes 1024 tSYS (sys-  
tem clock period) to resume normal operation. In other  
words, a dummy period will be inserted after wake-up. If  
the wake-up results from an interrupt acknowledgment,  
the actual interrupt subroutine execution will be delayed  
by one or more cycles. If the wake-up results in the next  
instruction execution, this will be executed immediately  
after the dummy period is finished.  
The functional unit chip reset status are shown below.  
Program Counter  
Interrupt  
000H  
Disable  
Clear. After master reset,  
WDT begins counting  
WDT  
Timer/Event Counter Off  
Input/Output Ports  
Stack Pointer  
Input mode  
Points to the top of the stack  
To minimize power consumption, all the I/O pins should  
be carefully managed before entering the HALT status.  
Reset  
V
D
D
There are three ways in which a reset can occur:  
m
0 . 0 1 F *  
·
RES reset during normal operation  
·
RES reset during HALT  
1
0
0
k
·
WDT time-out reset during normal operation  
R
E
S
1
0
k
The WDT time-out during HALT is different from other  
chip reset conditions, since it can perform a ²warm re -  
set² that resets only the program counter and SP, leav-  
ing the other circuits in their original state. Some regis-  
ters remain unchanged during other reset conditions.  
Most registers are reset to the ²initial condition² when  
the reset conditions are met. By examining the PDF and  
TO flags, the program can distinguish between different  
²chip resets².  
m
0 . 1 F *  
Reset Circuit  
Note:  
²*² Make the length of the wiring, which is con-  
nected to the RES pin as short as possible, to  
avoid noise interference.  
TO PDF  
RESET Conditions  
RES reset during power-up  
RES reset during normal operation  
RES wake-up HALT  
V
D
D
0
u
0
1
1
0
u
1
u
1
R
E
S
t
S
S
T
S
S
T
T
i
m
e
-
o
u
t
C
h
i
p
R
e
s
e
t
WDT time-out during normal operation  
WDT wake-up HALT  
Reset Timing Chart  
Note: ²u² means ²unchanged²  
To guarantee that the system oscillator is started and  
stabilized, the SST (System Start-up Timer) provides an  
extra-delay of 1024 system clock pulses when the sys-  
tem reset (power-up, WDT time-out or RES reset) or the  
system awakes from the HALT state.  
H
A
L
T
W
a
r
m
R
e
s
e
t
W
D
T
R
E
S
C
o
l
d
When a system reset occurs, the SST delay is added  
during the reset period. Any wake-up from HALT will en-  
able the SST delay.  
R
e
s
e
t
S
S
T
1
0
-
b
i
t
R
i
p
p
l
e
O
S
C
1
C
o
u
n
t
e
r
An extra option load time delay is added during system  
reset (power-up, WDT time-out at normal mode or RES  
reset).  
S
y
s
t
e
m
R
e
s
e
t
Reset Configuration  
Rev. 1.30  
13  
July 13, 2005